1. Field of the Invention
The present invention relates to the design of input/output (I/O) circuits for semiconductor chips, and more specifically to the design of an I/O circuit that provides two output modes. In a first mode, the output is tailored to drive an open drain bus, which requires an external termination on a bus line. In a second mode, the output functions as a totem pole output, which does not require an external termination.
2. Related Art
Until recently, transistor--transistor logic (TTL) has been the dominant interface standard for semiconductor integrated circuits. Under the TTL standard, an input or an output of at least 2.4 volts corresponds to a logic "1," whereas an input of not more that 0.8 volts and an output of not more than 0.4 volts corresponds to a logic "zero." However, following the recent reduction of power source voltages in semiconductor devices (for example, from 5 volts to 3.3 volts), a reduced voltage version of TTL has emerged, which is known as Low Voltage TTL (LVTTL). Under the LVTTL standard, a signal level definition is divided into a determination level (AC specification), and a final level (DC specification) to which the signal the signal finally arrives. According to the AC specification, an input or an output of at least 2.0 volts corresponds to a logic "1," and an output of not more than 0.8 volts corresponds to a logic "zero." According to the DC specification, an input or an output of at least 2.4 volts corresponds to a logic "1," and an input of not more than 0.8 volts and an output of not more than 0.4 volts corresponds to a logic "zero."
As computer systems require faster data transfer speeds between integrated circuits, the TTL and LVTLL interface standards are beginning to limit computer system performance. For example, the delay time in charging and discharging a typical 100 pF capacitance between the 2.4 and 0.4 volt thresholds is beginning to exceed required access times. Additionally, as switching speeds increase, the output waveform of a TTL or a LVTTL driver becomes distorted due to overshooting, undershooting, ringing and the like, resulting in erroneous level determinations.
To remedy this problem, computer designers are beginning to use the Gunning transceiver logic (GTL) standard for data transmission. The GTL standard is based upon an open drain bus. A driver for a GTL+ bus is illustrated in FIG. 1 (GTL+ is a variation of GTL). The circuit illustrated in FIG. 1 includes a pad 130, which is coupled to an output driver circuit and an input receiver circuit. Pad 130 is additionally coupled to bus line 136, which is terminated through resistor 135 to V.sub.TT 132. Note that V.sub.TT 132 is supplied by V.sub.TT regulator 134. Typical values for resistor 135 and V.sub.TT 132 are 50 ohms and 1.2 volts, respectively.
The GTL output driver circuit includes transistor 126, which can be used to pull pad 130 to a ground voltage. The control input of transistor 126 originates from slew rate control circuit 120. Slew rate control circuit 120 takes inputs from a signal to be outputted 122 and an output enable signal 124. Slew rate control circuit uses these two inputs to selectively activate transistor 126 depending upon the state of inputs 122 and 124. Slew rate control circuit 120 additionally controls the rate at which the voltage on pad 130 changes in order to reduce transient noise on bus line 136.
The GTL input receiver circuit includes a differential receiver 110, which has inputs coupled to pad 130 and V.sub.REF 112. Differential receiver 110 includes a differential amplifier that compares the voltage at pad 130 (V.sub.PAD) to V.sub.REF. V.sub.REF is typically 0.8 volts. Differential receiver 110 produces input signal 114, which is asserted to a high value if V.sub.PAD is above V.sub.REF. Otherwise, input signal 114 is asserted to a low value. Hence, a GTL output takes a value of not more than 0.4 volts for a logic "zero," and a value of greater than V.sub.TT =1.2 volts for a logic "1." In contrast, the input level takes a value of not more than V.sub.REF -50 mV=0.75 volts for a logic "zero," and a value greater than V.sub.REF -50 mV=0.85 volts for a logic "1."
GTL has a number of advantages. Because the impedance of the wiring, the drive transistor and the terminal resistor are all defined at the same level, reflection of an output signal does not easily occur. Furthermore, since the signal amplitude is small, the charge/discharge current does not increase in comparison with that of a TTL interface, even when the capacitive load of the wiring is great.
An enhanced GTL+ driver is illustrated in FIG. 2. The enhanced GTL+ driver differs from the GTL+ driver illustrated in FIG. 1 in that it has a pullup transistor 202 coupled between pad 130 and V.sub.CC. Pullup transistor 202 is controlled by turn-off control circuit 200. Turn-off control circuit 200 receives signal to be outputted 122 and output enable signal 124 as inputs. It activates pullup transistor 202 for one clock cycle when both signal to be outputted 122 and output enable signal 124 are asserted. Afterwards, turn-off control circuit 200 goes inactive, allowing termination resistor 135 and/or other bus devices to drive bus line 136.
In spite of the above-mentioned advantages of a GTL interface, GTL requires modifications to a computer system that can greatly increase cost. FIG. 3 illustrates a multiprocessor system using a GTL bus 330 to link together system components. More specifically, processor cartridge 310, processor cartridge 320 and core logic 340 are coupled to and communicate through GTL bus 330.
Processor cartridge 310 includes microprocessor 316, which interfaces to GTL bus 330. Microprocessor 316 may include a microprocessor such as the Pentium II, manufactured by the Intel Corporation of Santa Clara, Calif. Processor cartridge 310 is coupled to V.sub.REF regulator 312 and V.sub.TT regulator 314, which provide V.sub.REF and V.sub.TT, respectively for GTL interfaces on microprocessor 316. The input/output pads of microprocessor 316 are coupled to V.sub.TT through resistors 318.
Processor cartridge 320 includes microprocessor 326, which interfaces to GTL bus 330. Processor cartridge 320 is coupled to V.sub.REF regulator 322 and V.sub.TT regulator 324, which provide V.sub.REF and V.sub.TT, respectively for GTL interfaces on microprocessor 326. The input/output pads of microprocessor 326 are coupled to V.sub.TT through resistors 328.
Core logic 340 includes interfaces to peripheral buses and other system components. Core logic 340 additionally includes V.sub.REF regulator 344, which provides V.sub.REF for GTL receivers in core logic 340.
FIG. 4 illustrates a single processor configuration for the multiprocessor system illustrated in FIG. 3. The system illustrated in FIG. 4 is the same as the system illustrated in FIG. 3, except for the fact that termination card 400 is substituted for processor cartridge 320. Note that termination card 400 is also coupled to voltage regulator 324 and includes terminal resistors 328. This is because GTL bus 330 must remain terminated even if processor cartridge 320 is removed.
FIG. 5 illustrates a single processor system, which is the same as the configuration illustrated in FIG. 2, except for the fact that it does not have a termination card. Instead, the lines of GTL bus 330 are directly terminated through resistors 328 to V.sub.TT. In this configuration, the bus lines are permanently terminated.
The extra computer system components required for GTL communications add significantly to system cost. A separate regulator for V.sub.REF is required for each component receiving signals from GTL bus 330. Additionally, a separate voltage regulator for V.sub.TT is required at each end of GTL bus 330 to provide terminations for GTL bus 330.
The additional cost to implement GTL communications can be justified for high performance computing systems because people are willing to pay for improved performance. However, for cheaper computer systems,--especially sub-$1000 personal computers--people may be unwilling to pay the additional costs. Additionally, economies of scale make it expensive and impractical to produce two different microprocessor chips, one supporting a GTL interface and the other supporting a TTL or a LVTTL interface.
What is needed is a microprocessor chip that provides two modes of interfacing. A first mode supporting a high-performance open drain interface, and a second mode supporting a lower-cost TTL or LVTLL interface.
U.S. Pat. No. 5,530,379, entitled "Output Buffer Circuit that can Be Shared by a Plurality of Interfaces and a Semiconductor Device Using the Same," to Konishi et al. discloses an output driver for a random access memory, that supports two modes of operation, one as a GTL output driver and one as a LVTTL output driver. However, Konishi is not directed to the problem of reducing cost by eliminating bus terminations. Hence, Konishi does not disclose a method and an apparatus for eliminating a bus termination. Furthermore, Konishi discloses a complicated apparatus in which a pullup transistor is converted into an additional pulldown transistor, and Konishi does not disclose a slew rate control circuit, or a turn-off control circuit.